The present invention relates to a plasma display apparatus and a driving method thereof. More particularly, the present invention relates to a plasma display apparatus, the display luminance of which has been improved with a simple modification of the circuit, and a driving method thereof.
The plasma display apparatus (PDP apparatus) has been put to practical use as a flat display and is highly regarded as a thin high-luminance display. Among several types of the PDP apparatus, a three-electrode surface discharge AC type PDP apparatus is most generally used and is used as an example in the description below.
FIG. 1 is a block diagram that shows the rough structure of a conventional PDP apparatus. A video signal enters a display gray level adjustment circuit 4, is adjusted to a level appropriate to the gray level display, and is developed into the data of a subfield structure, which will be described later, in a video signal—subfield matching circuit 5. The video signal is also entered into an average luminance detection circuit 7 and the average luminance is detected. A subfield unit pulse number setting circuit 8 determines the number of sustain discharge pulses of each subfield based on the length of the period of a field calculated from the synchronization signal and the detected average luminance. This is performed because there is a limit to the power consumption in the PDP apparatus and the total number of sustain discharge pulses is decreased to prevent the power consumption from exceeding the limit value when the average luminance is high. A subfield process circuit 6 generates a switch timing signal for each operation period, which will be described later, according to the number of sustain discharge pulses of each subfield determined by the subfield unit pulse number setting circuit 8, and sends it to a drive waveform generation circuit 9. The drive waveform generation circuit 9 generates a voltage waveform to be applied to the sustain discharge electrode according to the above-mentioned switch timing signal and sends it to a sustain electrode drive circuit 2. Simultaneously, the subfield process circuit 6 reads the display data of each subfield from the video signal—subfield matching circuit 5 and sends it to a data drive circuit 3. The sustain electrode drive circuit 2 applies a voltage, of a waveform which will be described later, to the sustain discharge electrodes (X electrode and Y electrode) of a three-electrode surface discharge AC type plasma display panel 1, and the data drive circuit 3 synchronously applies a data voltage to the address electrode. In the three-electrode surface discharge AC type plasma display panel 1, X electrodes and Y electrodes that extend in one direction are arranged adjacently by turns, address electrodes that extend in the direction perpendicular thereto are arranged, and display pixels are formed at the crossings of a pair of the X electrode and the Y electrode and each address electrode. The X electrode and the Y electrode constitute a sustain discharge electrode, the X electrode is commonly connected, and receives an identical voltage waveform, and a sustain discharge pulse is commonly applied to the Y electrode, as well as a scan pulse is independently applied thereto. Moreover, the address electrode is designed so that an address pulse can be independently applied thereto.
FIG. 2 is a diagram that shows the drive waveforms of the PDP apparatus. The drive sequence of the PDP apparatus comprises a reset period in which all the display cells are set to a uniform state, an address period in which the display cell is set to a state corresponding to the display data, and a sustain discharge period in which the display cell is made to emit light according to the set state. As shown schematically, in the reset period, while the Y address electrode is being kept at 0V, a pulse of voltage Vaw is applied to the address electrode and a pulse of voltage Vw, to the X electrode. In this way, a reset discharge is caused to occur in all the display cells regardless of the previous display state, the generated charges are neutralized, and all the display cells enter a uniform state. In the address period, while voltage Vx is being applied to the X electrode, a scan pulse is sequentially applied with voltage—Vc being applied to the Y electrode. The scan pulse is overlapped by the voltage—Vc and becomes a pulse of voltage—Vy. In synchronization with the application of each scan pulse, a data voltage is applied to the address electrode. The data voltage is Va in a lit display cell and 0V in an unlit display cell. In this way, an address discharge is caused to occur in a lit display cell and different charges are accumulated on the X electrode and the Y electrode, and no charge is accumulated in an unlit display cell because no discharge is caused to occur. By performing this action to every Y electrode, all the display cells enter a state that corresponds to the display data. In the sustain discharge period, while voltage Ve is being applied to the address electrode, the sustain discharge pulse of voltage Vs is applied alternately to the Y electrode and the X electrode. When the first sustain discharge pulse is applied to the Y electrode, a sustain discharge is caused to occur in a lit display cell because the voltage due to the charges accumulated during the address period is added to the sustain discharge pulse, and this sustain discharge causes charges, which have the opposite polarity to the previous ones, to accumulate on the X electrode and the Y electrode, therefore, if another sustain discharge pulse is applied to the X electrode, a sustain discharge is caused to occur again. Repetition of these actions causes a sustain discharge to occur successively. On the other hand, since no charge is accumulated in an unlit display cell, no discharge is caused to occur even if a sustain discharge pulse is applied. This sustain discharge relates to the display and the luminance of the subfield is determined by the number of times of sustain discharges, that is, the length of the sustain discharge period.
As described above, it is possible only to control a display cell to emit light or not in the PDP apparatus and the intensity of light emission cannot be altered for each cell. Therefore, when the gray level display is performed, a display field is composed of plural subfields. FIG. 3 is a diagram that illustrates the subfield structure for gray level display. As shown schematically, one display field is composed of plural subfields (four in this case) SF1-SF4. Each subfield comprises a reset period R, an address period A, and a sustain discharge period S, and the length of the sustain discharge period S, that is, the luminance, is different. For example, the luminance ratio of SF1-SF4 is 8:4:2:1. A desired luminance of light emission can be obtained for each display cell by selecting the subfields that emit light in a display field. This example of the subfield structure can provide 16 levels, that is, 0 to 15. For a display cell of level 7, SF2, SF3, and SF4 are lit, and for a display cell of level 12, SF1 and SF2 are lit.
The conventional PDP apparatus is described above and various methods have been proposed, but a more detailed description will not be provided here because the detailed structures thereof are publicly known.
One of the characteristics of PDP apparatus inferior to the CRT tube TV is that the peak luminance is low. One of the reasons is that the proportion of the sustain discharge period that relates to the display luminance in a display field is small. As shown in FIG. 3, one display field is composed of plural subfields and each subfield has the reset period and the address period of the same length regardless of the length of the sustain discharge period. In the actual PDP apparatus, one display field has eight to ten subfields in order to attain a sufficient gray level display and suppress problems such as color false contour. Therefore the reset period and the address period, which do not relate to the display luminance, occupy a large proportion of a display field and a problem that a sufficient peak luminance cannot be obtained is caused because the sustain discharge period cannot be sufficiently lengthened.
In order to solve these problems, Japanese Unexamined Patent Publication (Kokai) No. 2000-347616 has disclosed a technique to realize an improvement in the comprehensive image qualities, such as the gray level, by controlling the information on the resolution of the displayed image. In the technique, the address process is performed simultaneously for n (n is an integer equal to two or larger) lines in a special subfield to shorten the address period to 1/n, and the luminance is improved by allocating the saved time to the sustain discharge period of each subfield. The above-mentioned publicly known document has also disclosed compensation of the lighting information data to retain the image information as long as possible for the n lines, to which the address process is performed simultaneously, by performing calculation between each of n display cells in the vertical direction.
In order to realize the technique disclosed in Japanese Unexamined Patent Publication (Kokai) No. 2000-347616, however, it is necessary to modify the circuit so that the address process can be performed simultaneously for n display lines, therefore, a problem that such modification will be complex is caused.